M01500 - SEMI M15 - Polished Wafer Defect Limits Table for Semi-Insulating Gallium Arsenide Wafers Revision:SEMI M15-0298 - Inactive 12-1109 (technical revision)

12-1109 (technical revision)

2  Surface scanners

本スタンダードは，global Silicon Wafer Committeeで技術的に承認されている。現版は2007年4月25日，global Audits and Reviews Subcommitteeにて発行が承認された。2007年6月にwww

Component Manager Support — Identifies the component-level operations needed to create

and 16 nm technology generations

M01500 - SEMI M15 - Polished Wafer Defect Limits Table for Semi-Insulating Gallium Arsenide Wafers Revision:SEMI M15-0298 - Inactive 12-1109 (technical revision)This document defines the maximum number of defects, by type, that an acceptable polished Semi Insulating Gallium Arsenide (GaAs) wafer may exhibit. Referenced SEMI Standards None.